Opportunities for FPGA Design Verification Engineer in Scottsdale, AZ
Your browser does not support JavaScript, or it is disabled. JavaScript must be enabled in order to view listings.
#Scottsdale #setdesign
Scottsdale AZ
Ability to analyze requirements, create test plan, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM * Familiarity with testing complex designs, code
Java script is not supported in this view, please click above for full page.
Opportunities for FPGA Design Verification Engineer in Scottsdale, AZ